1. Technical Field
This invention relates generally to the attachment of integrated circuit devices to printed circuit boards. More particularly, the invention relates to the attachment of semiconductor integrated circuit (IC) chips to printed circuit boards utilizing an integrated circuit chip carrier, wherein all signal and power connections are made via the integrated circuit integrated circuit chip carrier.
2. Background Art
Integrated circuit chips are readily incorporated into their intended working environments when the integrated circuit chip has been installed in an integrated circuit chip carrier. A typical chip carrier provides an interface between the integrated circuit chip and the circuit board by providing electrical interconnections to off-chip or external devices.
Organic substrates for use in chip carriers have been used and continue to be developed for many applications. These substrates are expected to replace ceramic substrates, particularly in chip carrier applications, due to improved electrical performance and lower cost. However, the use of a multi-layered interconnect structure, such as an organic chip carrier, for interconnecting a semiconductor chip to a printed circuit board in an electronic package introduces many challenges, one of which is the amount of space required between electrical signal circuits within the chip carrier.
As semiconductor chip input/output (I/O) counts increase beyond the capability of peripheral lead devices and as the trend towards semiconductor chip and printed circuit board miniaturization continues, area array interconnects are the preferred method for making large numbers of connections between a semiconductor chip and an organic chip carrier, and between the organic chip carrier and a printed circuit board.
A typical chip carrier includes a top surface and a bottom surface. (The terms xe2x80x9ctopxe2x80x9d and xe2x80x9cbottomxe2x80x9d are used only to differentiate between the two surfaces, and do not specifically refer to the orientation of the chip or carrier when the structure is mounted on the printed circuit board.) The top surface of the chip carrier has an array of bonding pads which are arranged in a pattern that corresponds to the pattern or xe2x80x9cfootprintxe2x80x9d of the input and output pads on the chip. The bottom surface of the chip carrier has a second set of bonding pads which are connected to the first set of bonding pads by through-vias. A through-via is a (usually) cylindrical hole extending through the thickness of the chip carrier and is lined with a material, such as copper, that acts both as an electrical and a thermal conductor. The through-via provides a path of electrical conduction between the chip and the electrical circuit patterns located within internal layers of the chip carrier. The drilling of through-vias in the carrier is a common approach used to provide signal, ground and power interconnection means.
However, drilling all through-vias utilizing an industry standard grid pattern, such as the Controlled Collapse Chip Connector (C4) solder ball grid, as would be necessary for complete signal, ground, and power interconnections, requires drilling on an extremely narrow pitch (e.g., a 9 mil or less pitch). In order to enable all signal wires to escape through the channels between the drilled holes, a narrow wire (e.g., less than 18 microns) would be required. Designs with such wiring typically result in very low usable product yields.
Other designs have been proposed which incorporate wiring channels and a sequential build process to separate the through-vias from signal circuits. The signal wires in these designs have widths as small as 14 microns. However, such wiring may not meet required resistance specifications. Also, in order to achieve the 14 micron wire width, the plating in the through-vias is necessarily very thin, on the order of 2-3 microns. This relatively thin plating results in deficiencies in the thermal and electrical properties of the through-via. The design approach taken in this invention results in the signal wire width being independent of the plated through hole (PTH) plating thickness.
Thus, there exists a need for an efficient and inexpensive way to increase the packaging density, the electrical performance, and the device reliability of a chip carrier structure. An electronic package that includes a multilayer interconnect structure such as an organic chip carrier, and that provides wiring channels through which electrical signals can be routed, can substantially increase the density of interconnections between the semiconductor chip and the organic chip carrier, and between the organic chip carrier and the printed circuit board. Furthermore, it can enable design of the electronic package to significantly improve electrical performance. It is believed that such a structure would constitute a significant art advancement.
The present invention provides a structure for a chip carrier which includes placement of through-vias in locations which are considered xe2x80x9coff-grid,xe2x80x9d that is, they are not in a location, when disposed in the interior of the chip carrier, defined by a typical grid coordinate or array pattern system. Relocating through-vias in this manner allows grouping of electrical signal traces into wiring channels which are placed between the through-vias. The use of wiring channels further allows for increased line widths, which result in corresponding increases in product reliability and yield.
The electrical through-via signals are returned to xe2x80x9con-gridxe2x80x9d locations (i.e. the array pattern required for further connection) within the multilayer structure using electrically conductive connectors, typically dog-bone shaped, within internal layers. Thus, the electrical signals are again in an array pattern arrangement when they exit the chip carrier from its top and bottom surfaces. The array pattern arrangement on the bottom surface may be similar to that of the top surface. Alternatively, the array pattern arrangement of the bottom surface may represent a significant difference from that of the top surface. For example, there may be an expansion or contraction of the array pattern of the top surface (e.g., a fan-out pattern or fan-in pattern, respectively). These transpositions may be rectilinear or radial, or some combination thereof. Further, a single through-via may connect to more than one microvia, or vice versa.
The return of the through-vias to array pattern locations can be accomplished utilizing blind vias drilled through an external dielectric layer which has been applied to the chip carrier after the through-vias have been drilled and plated. The external dielectric layer will tent and/or fill in the off-grid or non-array pattern through vias. Alternatively, these blind vias may be formed using techniques well known in the art, including laser ablating, plasma etching, mechanical drilling, or photo-imaging.
Generally, the present invention provides an integrated circuit carrier structure including a laminated assembly comprising: a first surface; a second surface substantially parallel to said first surface; an array of contact pads arranged in a first array pattern on said first surface; an array of contact pads arranged in a second array pattern on said second surface; through-vias within said structure for connecting respective contact pads on the first and second surfaces, wherein said through-vias are horizontally displaced from the array pattern on the first surface; and conductive elements which connect the contact pads with the through-vias.
The present invention also provides a printed circuit board assembly comprising: a semiconductor integrated circuit; a printed circuit board; an integrated circuit carrier for mounting the semiconductor integrated circuit to the printed circuit board comprising: a layered structure having a first surface and a second surface substantially parallel to said first surface; an array of contact pads arranged in a first array pattern on said first surface; an array of contact pads arranged in a second array pattern on said second surface; through-vias within said structure for connecting respective contact pads on the first and second surfaces, wherein said through-vias are horizontally displaced from the array pattern on the first surface for the purpose of maximizing available wiring channel volume; and conductive elements which connect the contact pads with the through-vias.
The present invention further provides a method of constructing an integrated circuit carrier structure with a laminated assembly, wherein the laminated assembly includes first and second substantially parallel surfaces, comprising: arranging an array of contact pads in a first array pattern on said first surface; arranging an array of contact pads in a second array pattern on said second surface; forming through-vias within said structure for connecting respective contact pads on the first and second surfaces, wherein said through-vias are horizontally displaced from the array pattern on the first surface; and incorporating conductive elements to connect the contact pads with the through-vias.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.